1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more specifically, to a technology of setting a mode register using a nonvolatile ferroelectric register so that data stored in the mode register may be maintained even when power is off.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
FIGS. 1 and 2 are diagrams illustrating the mode register setup process in a conventional semiconductor memory device.
In the conventional semiconductor memory device, if power is supplied to a chip and a power-up operation is completed (S1), clock signals CLK and /CLK are generated. Then, if the clock signals CLK and /CLK are enabled, volatile data are set in a mode register in response to a command signal (S2). Then, an active, write or read command is performed in response to data set in the mode register (S3). If power is re-supplied in a power-down state (S4), the mode register setting process is performed again.
FIG. 3 is a diagram of a volatile mode register 2 in the conventional semiconductor memory device.
The conventional mode register 2 stores volatile data on chip setting condition in each data region. That is, the mode register 2 sets a burst length, a burst type, a column address strobe latency, a test mode and a DLL (delay-locked loop) in each data region depending on addresses A0˜A14 applied from an address bus 1.
Here, the burst length is a unit to consecutively read and write various data at one time, and set as 1,2,4,8 or a full page. The burst type changes addresses with a sequential or interleave type when addresses are changed by the burst length.
The column address strobe latency represents in which clock data can be outputted after the read command. Here, the value of the column address strobe latency becomes 0 in the write mode. The test mode stores information on variables necessary for test. The DLL stores information on variables used when delay time is set.
However, in the conventional mode register 2, data stored in the mode register 2 are required to be reset whenever power is supplied to a system. As a result, the performance of the system is degraded, and the control of a chip is difficult.
Meanwhile, as the operation speed of a semiconductor memory device comprising the volatile mode register 2 increases gradually, noise reflection signals are generated in a transmission process of bus signals. To improve a characteristic of transmission signals by absorbing noise reflection signals, termination resistors are added to each bus.
The termination resistor is generally installed in a bus of an external board of a chip. As a result, the area of the board increases by configuration of extra termination circuits, and current may be leaked through termination resistors in a power-down mode.